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Config.h 6bbcaa0ba959cfcb3aaff398339fa09cce054fd6 (6bbcaa0b) Text, 7.03 KB
T8b949e// Copyright (C) 2024, Mark Qvist
T8b949e// This program is free software: you can redistribute it and/or modify
T8b949e// it under the terms of the GNU General Public License as published by
T8b949e// the Free Software Foundation, either version 3 of the License, or
T8b949e// (at your option) any later version.
T8b949e// This program is distributed in the hope that it will be useful,
T8b949e// but WITHOUT ANY WARRANTY; without even the implied warranty of
T8b949e// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
T8b949e// GNU General Public License for more details.
T8b949e// You should have received a copy of the GNU General Public License
T8b949e// along with this program. If not, see <https://www.gnu.org/licenses/>.
Tff7b72#Tff7b72include T8b949e"ROM.h"
Tff7b72#Tff7b72include T8b949e"Boards.h"
Tff7b72#Tff7b72ifndef CONFIG_H
Tff7b72#Tff7b72define CONFIG_H
Tff7b72#Tff7b72define MAJ_VERS 0x01
Tff7b72#Tff7b72define MIN_VERS 0x51
Tff7b72#Tff7b72define MODE_HOST 0x11
Tff7b72#Tff7b72define MODE_TNC 0x12
Tff7b72#Tff7b72define CABLE_STATE_DISCONNECTED 0x00
Tff7b72#Tff7b72define CABLE_STATE_CONNECTED 0x01
Tffa657uint8_t Te6edf3cable_state Tff7b72= Te6edf3CABLE_STATE_DISCONNECTEDTb4b4b4;
Tff7b72#Tff7b72define BT_STATE_NA 0xff
Tff7b72#Tff7b72define BT_STATE_OFF 0x00
Tff7b72#Tff7b72define BT_STATE_ON 0x01
Tff7b72#Tff7b72define BT_STATE_PAIRING 0x02
Tff7b72#Tff7b72define BT_STATE_CONNECTED 0x03
Tffa657uint8_t Te6edf3bt_state Tff7b72= Te6edf3BT_STATE_NATb4b4b4;
Tffa657uint32_t Te6edf3bt_ssp_pin Tff7b72= T79c0ff0Tb4b4b4;
Tffa657bool Te6edf3bt_ready Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3bt_enabled Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3bt_allow_pairing Tff7b72= Tffa657falseTb4b4b4;
Tff7b72#Tff7b72define M_FRQ_S 27388122
Tff7b72#Tff7b72define M_FRQ_R 27388061
Tffa657bool Te6edf3console_active Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3modem_installed Tff7b72= Tffa657falseTb4b4b4;
Tff7b72#Tff7b72define MTU 508
Tff7b72#Tff7b72define SINGLE_MTU 255
Tff7b72#Tff7b72define HEADER_L 1
Tff7b72#Tff7b72define MIN_L 1
Tff7b72#Tff7b72define CMD_L 64
Tffa657bool Te6edf3mw_radio_online Tff7b72= Tffa657falseTb4b4b4;
Tff7b72#Tff7b72define eeprom_addr(a) (a+EEPROM_OFFSET)
Tff7b72#Tff7b72if (MODEM == SX1262 || MODEM == SX1280) && defined(NRF52840_XXAA)
Te6edf3SPIClass Td2a8ffspiModemTb4b4b4(Te6edf3NRF_SPIM2Tb4b4b4, Te6edf3pin_misoTb4b4b4, Te6edf3pin_sclkTb4b4b4, Te6edf3pin_mosiTb4b4b4)Tb4b4b4;
Tff7b72#Tff7b72endif
T8b949e// MCU independent configuration parameters
Tff7b72const Tffa657long Te6edf3serial_baudrate Tff7b72= T79c0ff115200Tb4b4b4;
T8b949e// SX1276 RSSI offset to get dBm value from
T8b949e// packet RSSI register
Tff7b72const Tffa657int Te6edf3rssi_offset Tff7b72= T79c0ff157Tb4b4b4;
T8b949e// Default LoRa settings
Tff7b72#Tff7b72define PHY_HEADER_LORA_SYMBOLS 20
Tff7b72#Tff7b72define PHY_CRC_LORA_BITS 16
Tff7b72#Tff7b72define LORA_PREAMBLE_SYMBOLS_MIN 18
Tff7b72#Tff7b72define LORA_PREAMBLE_TARGET_MS 24
Tff7b72#Tff7b72define LORA_PREAMBLE_FAST_DELTA 18
Tff7b72#Tff7b72define LORA_FAST_THRESHOLD_BPS 30E3
Tff7b72#Tff7b72define LORA_LIMIT_THRESHOLD_BPS 60E3
Tffa657long Te6edf3lora_preamble_symbols Tff7b72= Te6edf3LORA_PREAMBLE_SYMBOLS_MINTb4b4b4;
Tffa657long Te6edf3lora_preamble_time_ms Tff7b72= T79c0ff0Tb4b4b4;
Tffa657long Te6edf3lora_header_time_ms Tff7b72= T79c0ff0Tb4b4b4;
Tffa657float Te6edf3lora_symbol_time_ms Tff7b72= T79c0ff0.0Tb4b4b4;
Tffa657float Te6edf3lora_symbol_rate Tff7b72= T79c0ff0.0Tb4b4b4;
Tffa657float Te6edf3lora_us_per_byte Tff7b72= T79c0ff0.0Tb4b4b4;
Tffa657bool Te6edf3lora_low_datarate Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3lora_limit_rate Tff7b72= Tffa657falseTb4b4b4;
T8b949e// CSMA Parameters
Tff7b72#Tff7b72define CSMA_SIFS_MS 0
Tff7b72#Tff7b72define CSMA_POST_TX_YIELD_SLOTS 3
Tff7b72#Tff7b72define CSMA_SLOT_MAX_MS 100
Tff7b72#Tff7b72define CSMA_SLOT_MIN_MS 24
Tff7b72#Tff7b72define CSMA_SLOT_MIN_FAST_DELTA 18
Tff7b72#Tff7b72define CSMA_SLOT_SYMBOLS 12
Tff7b72#Tff7b72define CSMA_CW_BANDS 4
Tff7b72#Tff7b72define CSMA_CW_MIN 0
Tff7b72#Tff7b72define CSMA_CW_PER_BAND_WINDOWS 15
Tff7b72#Tff7b72define CSMA_BAND_1_MAX_AIRTIME 7
Tff7b72#Tff7b72define CSMA_BAND_N_MIN_AIRTIME 85
Tff7b72#Tff7b72define CSMA_INFR_THRESHOLD_DB 12
Tffa657bool Te6edf3interference_detected Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3avoid_interference Tff7b72= Tffa657trueTb4b4b4;
Tffa657int Te6edf3csma_slot_ms Tff7b72= Te6edf3CSMA_SLOT_MIN_MSTb4b4b4;
Tffa657unsigned Tffa657long Te6edf3difs_ms Tff7b72= Te6edf3CSMA_SIFS_MS Tff7b72+ T79c0ff2Tff7b72*Te6edf3csma_slot_msTb4b4b4;
Tffa657unsigned Tffa657long Te6edf3difs_wait_start Tff7b72= T79c0ff-1Tb4b4b4;
Tffa657unsigned Tffa657long Te6edf3cw_wait_start Tff7b72= T79c0ff-1Tb4b4b4;
Tffa657unsigned Tffa657long Te6edf3cw_wait_target Tff7b72= T79c0ff-1Tb4b4b4;
Tffa657unsigned Tffa657long Te6edf3cw_wait_passed Tff7b72= T79c0ff0Tb4b4b4;
Tffa657int Te6edf3csma_cw Tff7b72= T79c0ff-1Tb4b4b4;
Tffa657uint8_t Te6edf3cw_band Tff7b72= T79c0ff1Tb4b4b4;
Tffa657uint8_t Te6edf3cw_min Tff7b72= T79c0ff0Tb4b4b4;
Tffa657uint8_t Te6edf3cw_max Tff7b72= Te6edf3CSMA_CW_PER_BAND_WINDOWSTb4b4b4;
T8b949e// LoRa settings
Tffa657int Te6edf3lora_sf Tff7b72= T79c0ff0Tb4b4b4;
Tffa657int Te6edf3lora_cr Tff7b72= T79c0ff5Tb4b4b4;
Tffa657int Te6edf3lora_txp Tff7b72= T79c0ff0xFFTb4b4b4;
Tffa657uint32_t Te6edf3lora_bw Tff7b72= T79c0ff0Tb4b4b4;
Tffa657uint32_t Te6edf3lora_freq Tff7b72= T79c0ff0Tb4b4b4;
Tffa657uint32_t Te6edf3lora_bitrate Tff7b72= T79c0ff0Tb4b4b4;
T8b949e// Operational variables
Tffa657bool Te6edf3radio_locked Tff7b72= Tffa657trueTb4b4b4;
Tffa657bool Te6edf3radio_online Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3community_fw Tff7b72= Tffa657trueTb4b4b4;
Tffa657bool Te6edf3hw_ready Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3radio_error Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3disp_ready Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3pmu_ready Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3promisc Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3implicit Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3memory_low Tff7b72= Tffa657falseTb4b4b4;
Tffa657uint8_t Te6edf3implicit_l Tff7b72= T79c0ff0Tb4b4b4;
Tffa657uint8_t Te6edf3op_mode Tff7b72= Te6edf3MODE_HOSTTb4b4b4;
Tffa657uint8_t Te6edf3model Tff7b72= T79c0ff0x00Tb4b4b4;
Tffa657uint8_t Te6edf3hwrev Tff7b72= T79c0ff0x00Tb4b4b4;
Tff7b72#Tff7b72define NOISE_FLOOR_SAMPLES 64
Tffa657int Te6edf3noise_floor Tff7b72= T79c0ff-292Tb4b4b4;
Tffa657int Te6edf3current_rssi Tff7b72= T79c0ff-292Tb4b4b4;
Tffa657int Te6edf3last_rssi Tff7b72= T79c0ff-292Tb4b4b4;
Tffa657uint8_t Te6edf3last_rssi_raw Tff7b72= T79c0ff0x00Tb4b4b4;
Tffa657uint8_t Te6edf3last_snr_raw Tff7b72= T79c0ff0x80Tb4b4b4;
Tffa657uint8_t Te6edf3seq Tff7b72= T79c0ff0xFFTb4b4b4;
Tffa657uint16_t Te6edf3read_len Tff7b72= T79c0ff0Tb4b4b4;
T8b949e// Incoming packet buffer
Tffa657uint8_t Te6edf3pbufTb4b4b4[Te6edf3MTUTb4b4b4]Tb4b4b4;
T8b949e// KISS command buffer
Tffa657uint8_t Te6edf3cmdbufTb4b4b4[Te6edf3CMD_LTb4b4b4]Tb4b4b4;
T8b949e// LoRa transmit buffer
Tffa657uint8_t Te6edf3tbufTb4b4b4[Te6edf3MTUTb4b4b4]Tb4b4b4;
Tffa657uint32_t Te6edf3stat_rx Tff7b72= T79c0ff0Tb4b4b4;
Tffa657uint32_t Te6edf3stat_tx Tff7b72= T79c0ff0Tb4b4b4;
Tff7b72#Tff7b72define STATUS_INTERVAL_MS 3
Tff7b72#Tff7b72if MCU_VARIANT == MCU_ESP32 || MCU_VARIANT == MCU_NRF52
Tff7b72#Tff7b72define DCD_SAMPLES 2500
Tff7b72#Tff7b72define UTIL_UPDATE_INTERVAL_MS 1000
Tff7b72#Tff7b72define UTIL_UPDATE_INTERVAL (UTIL_UPDATE_INTERVAL_MSTff7b72/Tff7b72STATUS_INTERVAL_MS)
Tff7b72#Tff7b72define AIRTIME_LONGTERM 3600
Tff7b72#Tff7b72define AIRTIME_LONGTERM_MS (AIRTIME_LONGTERM*1000)
Tff7b72#Tff7b72define AIRTIME_BINLEN_MS (STATUS_INTERVAL_MS*DCD_SAMPLES)
Tff7b72#Tff7b72define AIRTIME_BINS ((AIRTIME_LONGTERM*1000)Tff7b72/Tff7b72AIRTIME_BINLEN_MS)
Tffa657bool Te6edf3util_samplesTb4b4b4[Te6edf3DCD_SAMPLESTb4b4b4]Tb4b4b4;
Tffa657uint16_t Te6edf3airtime_binsTb4b4b4[Te6edf3AIRTIME_BINSTb4b4b4]Tb4b4b4;
Tffa657float Te6edf3longterm_binsTb4b4b4[Te6edf3AIRTIME_BINSTb4b4b4]Tb4b4b4;
Tffa657int Te6edf3dcd_sample Tff7b72= T79c0ff0Tb4b4b4;
Tffa657float Te6edf3local_channel_util Tff7b72= T79c0ff0.0Tb4b4b4;
Tffa657float Te6edf3total_channel_util Tff7b72= T79c0ff0.0Tb4b4b4;
Tffa657float Te6edf3longterm_channel_util Tff7b72= T79c0ff0.0Tb4b4b4;
Tffa657float Te6edf3airtime Tff7b72= T79c0ff0.0Tb4b4b4;
Tffa657float Te6edf3longterm_airtime Tff7b72= T79c0ff0.0Tb4b4b4;
Tff7b72#Tff7b72define current_airtime_bin(void) (millis()%AIRTIME_LONGTERM_MS)Tff7b72/Tff7b72AIRTIME_BINLEN_MS
Tff7b72#Tff7b72endif
Tffa657float Te6edf3st_airtime_limit Tff7b72= T79c0ff0.0Tb4b4b4;
Tffa657float Te6edf3lt_airtime_limit Tff7b72= T79c0ff0.0Tb4b4b4;
Tffa657bool Te6edf3airtime_lock Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3stat_signal_detected Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3stat_signal_synced Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3stat_rx_ongoing Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3dcd Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3dcd_led Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3dcd_waiting Tff7b72= Tffa657falseTb4b4b4;
Tffa657long Te6edf3dcd_wait_until Tff7b72= T79c0ff0Tb4b4b4;
Tffa657uint16_t Te6edf3dcd_count Tff7b72= T79c0ff0Tb4b4b4;
Tffa657uint16_t Te6edf3dcd_threshold Tff7b72= T79c0ff2Tb4b4b4;
Tffa657uint32_t Te6edf3status_interval_ms Tff7b72= Te6edf3STATUS_INTERVAL_MSTb4b4b4;
Tffa657uint32_t Te6edf3last_status_update Tff7b72= T79c0ff0Tb4b4b4;
Tffa657uint32_t Te6edf3last_dcd Tff7b72= T79c0ff0Tb4b4b4;
T8b949e// Power management
Tff7b72#Tff7b72define BATTERY_STATE_UNKNOWN 0x00
Tff7b72#Tff7b72define BATTERY_STATE_DISCHARGING 0x01
Tff7b72#Tff7b72define BATTERY_STATE_CHARGING 0x02
Tff7b72#Tff7b72define BATTERY_STATE_CHARGED 0x03
Tffa657bool Te6edf3battery_installed Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3battery_indeterminate Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3external_power Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3battery_ready Tff7b72= Tffa657falseTb4b4b4;
Tffa657float Te6edf3battery_voltage Tff7b72= T79c0ff0.0Tb4b4b4;
Tffa657float Te6edf3battery_percent Tff7b72= T79c0ff0.0Tb4b4b4;
Tffa657uint8_t Te6edf3battery_state Tff7b72= T79c0ff0x00Tb4b4b4;
Tffa657uint8_t Te6edf3display_intensity Tff7b72= T79c0ff0xFFTb4b4b4;
Tffa657uint8_t Te6edf3display_addr Tff7b72= T79c0ff0xFFTb4b4b4;
Tff7b72volatile Tffa657bool Te6edf3display_updating Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3display_blanking_enabled Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3display_diagnostics Tff7b72= Tffa657trueTb4b4b4;
Tffa657bool Te6edf3device_init_done Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3eeprom_ok Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3firmware_update_mode Tff7b72= Tffa657falseTb4b4b4;
Tffa657bool Te6edf3serial_in_frame Tff7b72= Tffa657falseTb4b4b4;
T8b949e// Boot flags
Tff7b72#Tff7b72define START_FROM_BOOTLOADER 0x01
Tff7b72#Tff7b72define START_FROM_POWERON 0x02
Tff7b72#Tff7b72define START_FROM_BROWNOUT 0x03
Tff7b72#Tff7b72define START_FROM_JTAG 0x04
Tff7b72#Tff7b72endif
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